CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 99

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.9.19
1.9.20
Datasheet
C0DTAEW - Channel 0 DRAM Rank Throttling Active Event
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Programmable Event weights are input into the averaging filter. Each Event weight is an
normalized 8-bit value that the BIOS must program. The BIOS must account for burst
length and 1N/2N rule considerations. It is also possible for BIOS to take into account
loading variations of memory caused as a function of memory types and population of
ranks. GMCH implements four independent filters, one per rank. During a given clock,
GMCH asserts a command to the DRAM (via CSB assertion). Based on the command
type, one of the weights specified in this register is added to the appropriate weight
specified in C0DTPEW and input to the filter. All bits in this register can be locked by the
DTLOCK bit in the C0DTC register.
C1DRB0 - Channel 1 DRAM Rank Boundary Address 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRB0.
63:48
47:40
39:32
31:24
23:16
15:10
15:8
9:0
7:0
Bit
Bit
Access
Access
RW-L
RW-L
RW-L
RW-L
RW-L
RW-L
RW-L
RO
RO
000000b
Default
Default
Value
0000h
Value
000h
00h
00h
00h
00h
00h
00h
Reserved
Channel 1 DRAM Rank Boundary Address 0
(C1DRBA0)
See C0DRB0.
This register is locked by Intel ME stolen Memory lock.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0/0/0/MCHBAR
2AC-2B3h
0000000000000000h
64 bits
0/0/0/MCHBAR
600-601h
0000h
RW-L; RO
16 bits
RO; RW-L
Description
Description
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