CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 203

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CP80617004119AES LBU3

Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet

Specifications of CP80617004119AES LBU3

Lead Free Status / RoHS Status
Compliant
Processor Configuration Registers
1.14.2
Datasheet
PVCCAP1 - Port VC Capability Register 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Describes the configuration of PCI Express Virtual Channels associated with this port.
31:12
11:10
9:8
6:4
2:0
Bit
7
3
Access
RO
RO
RO
RO
RO
RO
RO
Default
00000h
Value
000b
000b
00b
00b
0b
0b
Reserved
Reserved for Port Arbitration Table Entry Size ()
Reserved
Reserved for Reference Clock ()
Reserved
Low Priority Extended VC Count (LPEVCC)
Indicates the number of (extended) Virtual Channels in
addition to the default VC belonging to the low-priority
VC (LPVC) group that has the lowest priority with respect
to other VC resources in a strict-priority VC Arbitration.
The value of 0 in this field implies strict VC arbitration.
Reserved
Extended VC Count (EVCC:
addition to the default VC supported by the device.
0/1/0/MMR
104-107h
00000000h
32 bits
Reserved
Indicates the number of (extended) Virtual Channels in
RO
Description
203

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