CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 122

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.10.8
122
HWTHROTCTRL1 - Hardware Throttle Control 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
2:1
Bit
7
6
5
4
3
0
Access
RW-O
RW-L
RW-L
RW-L
RW-L
RO
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
Internal Thermal Hardware Throttling Enable (ITHTE)
This bit is a master enable for internal thermal sensor-based
hardware throttling:
0 = Hardware actions via the internal thermal sensor are
1 = Hardware actions via the internal thermal sensor are
Reserved
Use Direct Catastrophic Trip for HOC (UDCTHOC)
0 = Thermometer comparison to catastrophic trip value is
1 = Catastrophic trip output of DTS circuit is used to control
Throttle Zone Selection (TZS)
This bit determines what temperature zones will enable
auto-throttling. This register applies to internal thermal
sensor throttling. Lockable by bit0 of this register.
0 = Hot, Aux2, and Catastrophic.
1 = Hot and Catastrophic.
Halt on Catastrophic (HOC)
When this bit is set, THRMTRIPB is asserted on catastrophic
trip to bring the platform down. A system reboot is required
to bring the system out of a halt from the thermal sensor.
Once the catastrophic trip point is reached, THRMTRIPB will
stay asserted even if the catastrophic trip deasserts before
the platform is shut down.
Reserved
Hardware Throttling Lock Bit (HTL)
This bit locks Bits 7:1 of this register. When this bit is set to
a one, the register bits are locked. It may only be set to a 0
by a hardware reset. Writing a 0 to this bit has no effect.
0/0/0/MCHBAR
101Ch
00h
RW-L; RO; RW-O
8 bits
disabled.
enabled.
used to control THRMTRIPB.
THRMTRIPB.
Processor Configuration Registers
Description
Datasheet