CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 293

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.18.30
Datasheet
FRCD_REG - Fault Recording Registers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Registers to record DMA-remapping fault information when primary fault logging is
active. Hardware reports the number and location of fault recording registers through
the Capability register. This register is relevant only for primary fault logging. These
registers are sticky and can be cleared only through powergood reset or via software
clearing the RW1C fields by writing a 1.
125:124
123:104
103:96
95:80
79:64
127
126
Bit
Access
RWC-P
RO-P
RO-P
RO-P
RO-P
RO
RO
0000000000
0000000000
Default
0000h
0000h
Value
00b
00h
0h
0h
b
Fault (F)
Hardware sets this field to indicate a fault is logged in this
Fault Recording register.
The F field is set by hardware after the details of the fault
is recorded in the PADDR, SID, FR and T fields. When this
field is set, hardware may collapse additional faults from
the same requestor (SID). Software writes the value read
from this field to clear it.
Type (T)
Type of the faulted DMA request.
0 = DMA write
1 = DMA read request. This field is relevant only when the
Address Type (AT)
This field captures the AT field from the faulted DMA
request. Hardware implementations not supporting
Device- IOTLBs (DI field Clear in Extended Capability
register) treat this field as RsvdZ.
When supported, this field is valid only when the F field is
Set, and when the fault reason (FR) indicates one of the
DMA-remapping fault conditions.
Reserved
Fault Reason (FR)
Reason for the fault. Appendix B enumerates the various
translation fault reason encodings. This field is relevant
only when the F field is set.
Reserved
Source Identifier (SID)
Requester-id of the faulted DMA request. This field is
relevant only when the F field is set.
0/0/0/VC0PREMAP
200-20Fh
00000000000000000000000000000000h
RWC-P; RO-P; RO
128 bits
(Sheet 1 of 2)
F field is set.
Description
293