CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 56

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.8.12
56
PXPEPBAR - PCI Express Egress Port Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the PCI Express Egress Port MMIO Configuration space.
There is no physical memory within this 4-KB window that can be addressed. The 4 KB
reserved by this register does not alias to any PCI 3.0-compliant memory mapped
space. On reset, the EGRESS port MMIO configuration space is disabled and must be
enabled by writing a 1 to PXPEPBAREN [Dev 0, Offset 40h, Bit 0].
All the bits in this register are locked in Intel TXT mode.
63:36
35:12
11:1
Bit
0
Access
RW-L
RW-L
RO
RO
0000000h
000000h
Default
Value
000h
0b
Reserved
PCI Express Egress Port MMIO Base Address
(PXPEPBAR)
This field corresponds to Bits 35:12 of the base address PCI
Express Egress Port MMIO configuration space. BIOS will
program this register resulting in a base address for a 4-KB
block of contiguous memory address space. This register
ensures that a naturally aligned 4-KB space is allocated
within the first 64 GB of addressable memory space. System
Software uses this base address to program the processor
MMIO register set. All the bits in this register are locked in
Intel VT-d mode.
Reserved
PXPEPBAR Enable (PXPEPBAREN)
0 = PXPEPBAR is disabled and does not claim any memory
1 = PXPEPBAR memory mapped accesses are claimed and
This register is locked by Intel VT-d.
Encoding
0/0/0/PCI
40-47h
0000000000000000h
RW-L; RO
64 bits
decoded appropriately
0b
1b
PXPEPBAR is disabled
PXPEPBAR is enabled
Processor Configuration Registers
Description
Description
Datasheet