CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 24
CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
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Note:
With Intel VT-d enabling configuration, there are exceptions to this rule:
Some of the MMIO Bars may be mapped to this range or to the range above TOUUD.
There are sub-ranges within the PCI Memory address range defined as APIC
Configuration Space, MSI Interrupt Space, and High BIOS Address Range. The
exceptions listed above for internal graphics and the PCI Express ports must not
overlap with these ranges.
1. Addresses decoded to the memory mapped window to Graphics Intel VT-d remap
2. Addresses decoded to the memory mapped window to DMI VC1 Intel VT-d remap
3. Addresses decoded to the memory mapped window to PEG/DMI/Intel ME VC0 Intel
4. TCm accesses (to Intel ME stolen memory) from PCH do not go through Intel VT-d
engine registers (GFXVTBAR)
engine registers (DMIVC1BAR)
VT-d remap engine registers (VTDPVC0BAR)
remap engines.
Processor Configuration Registers
Datasheet
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