CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 287

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.18.26
1.18.27
Datasheet
IEUADDR_REG - Invalidation Event Upper Address
Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the Invalidation Event interrupt message upper address. This
register is treated as RsvdZ by implementations reporting both Queued Invalidation
(QI) and Extended Interrupt Mode (EIM) as not supported in the Extended Capability
register.
IRTA_REG - Interrupt Remapping Table Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register providing the base address of Interrupt remapping table. This register is
treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not
supported in the Extended Capability register.
63:12
31:0
Bit
Bit
Access
Access
RW
RW
00000000
00000000
Default
Default
00000h
Value
Value
h
Message Upper Address (MUA)
Hardware implementations supporting Queued Invalidations
and Extended Interrupt Mode are required to implement this
register. Hardware implementations not supporting Queued
Invalidations and Extended Interrupt Mode may treat this
field as RSVD.
Interrupt Remapping Table Address (IRTA)
This field points to the base interrupt remapping table.
Hardware ignores and does not implement 63:HAW, where
HAW is the host address width.
Reads of this field returns last programmed to it.
0/0/0/VC0PREMAP
AC-AFh
00000000h
RW
32 bits
0/0/0/VC0PREMAP
B8-BFh
0000000000000000h
RO; RW
64 bits
(Sheet 1 of 2)
Description
Description
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