CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 106

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.9.30
106
C1CKECTRL - Channel 1 CKE Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 1 CKE Controls
31:28
26:24
19:17
16:14
Bit
27
23
22
21
20
Access
RW-L
RW-L
RW-L
RW-L
RW
RW
RW
RO
RO
Default
Value
000b
000b
000b
0h
0b
0b
0b
0b
0b
Reserved
start the self-refresh exit sequence (sd1_cr_srcstart)
This configuration register indicates the request to start the
self-refresh exit sequence
CKE pulse width requirement in high phase
(sd1_cr_cke_pw_hl_safe)
This configuration register indicates CKE pulse width
requirement in high phase.
Corresponds to tCKE (high) at DDR Spec.
Rank 3 Population (sd1_cr_rankpop3)
0: Rank 3 not populated
1: Rank 3 populated
This register is locked by Intel ME stolen Memory lock.
Rank 2 Population (sd1_cr_rankpop2)
0: Rank 2 not populated
1: Rank 2 populated
This register is locked by Intel ME stolen Memory lock.
Rank 1 Population (sd1_cr_rankpop1)
0: Rank 1 not populated
1: Rank 1 populated
This register is locked by Intel ME stolen Memory lock.
Rank 0 Population (sd1_cr_rankpop0)
Rank 0 not populated
Rank 0 populated
This register is locked by Intel ME stolen Memory lock.
CKE pulse width requirement in low phase
(sd1_cr_cke_pw_lh_safe)
This configuration register indicates CKE pulse width
requirement in low phase.
Corresponds to tCKE (low) at DDR Spec.
Reserved
0/0/0/MCHBAR
660-663h
00000800h
RW; RW-L; RO
32 bits
(Sheet 1 of 2)
Processor Configuration Registers
Description
Datasheet