CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 146

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.12
1.12.1
146
C3/C6 EntryTimers
Self-Refresh Channel Status
PM Memory Subsystem
Power Management Configuration
Register Name
Device 0 MCHBAR ACPI Power Management
Controls
C3C6ET - C3/C6 EntryTimers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:30
29:22
21:16
15:14
13:6
5:0
Bit
Access
RW
RW
RO
RO
RO
RO
C3C6ET
SLFRCS
DSLFRC
PMCFG
Register
Symbol
Default
Value
00b
00h
00h
00b
00h
00h
1200
1211
120C
1210
Register
Reserved
C6 Entry Timer (C6ET)
Dual purpose timer in 64 core clock granularity.
Number of host clocks (133 MHz) to wait between last
snoop from PEG, DMI or GFX to allowing (C6) entry from
the processor.
MSIs, for the purpose of this register, are handled as
snoops.
Reserved
Reserved
C3 Entry Timer (C3ET)
Dual purpose timer in 64 core clock granularity.
Number of host clocks (133 MHz) to wait between last
snoop from PEG, DMI or GFX to allowing (C3) entry from
the CPU.
MSIs, for the purpose of this register, are handled as
snoops.
Reserved
0/0/0/MCHBAR
1200-1203h
00000000h
RO; RW
32 bits
Start
00h:0 * 64 = 0 host clocks
FFh:255 * 64 = 16320 host clocks
00h:0 * 64 = 0 µs
FFh:255 * 64 = 16320 host clocks
1203
1212
120D
1210
Register
End
Processor Configuration Registers
Description
00000000h
0000h
0300h
04h
Default
Value
RW; RO
RW1C-S; RO
RO; RW
RW; RW-S
Access
Datasheet