CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 205

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.14.5
Datasheet
VC0RCAP - VC0 Resource Capability
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:24
22:16
14:8
7:0
Bit
23
15
Access
RO
RO
RO
RO
RO
RO
Default
Value
00h
00h
00h
01h
0b
0b
Reserved for Port Arbitration Table Offset
Reserved
Reserved for Maximum Time Slots
Reject Snoop Transactions (RSNPT)
0: Transactions with or without the No Snoop bit set
within the TLP header are allowed on this VC.
1: When Set, any transaction for which the No Snoop
attribute is applicable but is not Set within the TLP
Header is rejected as an Unsupported Request
Reserved
Port Arbitration Capability (PAC)
Port Arbitration Capability – Indicates types of Port
Arbitration supported by the VC resource. This field is
valid for all Switch Ports, Root Ports that support peer-to
to-peer traffic, and RCRBs, but not for PCI Express
Endpoint devices or Root Ports that do not support peer
to peer traffic. Each bit location within this field
corresponds to a Port Arbitration Capability defined
below. When more than one bit in this field is Set, it
indicates that the VC resource can be configured to
provide different arbitration services. Software selects
among these capabilities by writing to the Port
Arbitration Select field (see below). Defined bit positions
are:
Bit 0 Non-configurable hardware-fixed arbitration
scheme, e.g., Round Robin (RR)
Bit 1 Weighted Round Robin (WRR) arbitration with 32
phases
Bit 2 WRR arbitration with 64 phases
Bit 3 WRR arbitration with 128 phases
Bit 4 Time-based WRR with 128 phases
Bit 5 WRR arbitration with 256 phases
Bits 6-7 Reserved MCH default indicates “Non-
configurable hardware-fixed arbitration scheme”.
0/1/0/MMR
110-113h
00000001h
32 bits
RO
Description
205