CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 275

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.18.10
1.18.11
Datasheet
FEDATA_REG - Fault Event Data Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the interrupt message data.
FEADDR_REG - Fault Event Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the interrupt message address.
31:16
15:0
31:2
1:0
Bit
Bit
Access
Access
RW
RW
RO
RO
00000000h
Default
Default
Value
Value
0000h
0000h
0h
Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit
MSI data fields.
Hardware implementations supporting only 16-bit MSI data
may treat this field as read-only (0).
Interrupt Message Data (ID)
Data value in the fault-event interrupt message.
RST/
PWR
Core
Core
0/0/0/VC0PREMAP
3C-3Fh
00000000h
RO; RW
32 bits
0/0/0/VC0PREMAP
40-43h
00000000h
RO; RW
32 bits
Message Address (MA)
When fault events are enabled, the contents of
this register specify the DWORD aligned address
(Bits 31:2) for the MSI memory write
transaction.
Reserved
Description
Description
275