CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 239

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.16.22
Datasheet
MGGC - Processor Graphics Control Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
All the Bits in this register are Intel TXT lockable.
15:12
11:8
Bit
Access
RO
RO
Default
Value
0h
0h
Reserved
GTT Graphics Memory Size (GGMS)
This field is used to select the amount of Main Memory that
is pre-allocated to support the Internal Graphics Translation
Table. The BIOS ensures that memory is pre-allocated only
when Internal graphics is enabled.
GSM is assumed to be a contiguous physical DRAM space
with DSM, and BIOS needs to allocate a contiguous memory
chunk. Hardware will drive the base of GSM from DSM only
using the GSM size programmed in the register.
are not claimed.
for GTT.
GTT.
MB of Global GTT and 1 MB for Shadow GTT.
1.5 MB of Global GTT and 1.5 MB for Shadow GTT.
MB of Global GTT and 2 MB for Shadow GTT.
All unspecified encodings of this register field are reserved,
hardware functionality is not guaranteed if used. This
register is locked and becomes Read Only when the D_LCK
bit in the SMRAM register is set.
0h:No memory pre-allocated. GTT cycles (Mem and IO)
1h:No Intel® VT-d mode, 1 MB of memory pre-allocated
3h:No Intel VT-d mode, 2 MB of memory pre-allocated for
9h:Intel VT-d mode, 2 MB of memory pre-allocated for 1
Ah:Intel VT-d mode, 3 MB of memory pre-allocated for
Bh:Intel VT-d mode, 4 MB of memory pre-allocated for 2
0/2/0/PCI
52-53h
0030h
RO
16 bits
(Sheet 1 of 2)
Description
239