CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 208

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.14.8
1.14.9
208
PEGSSTS - PCI Express-G Sequence Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PCI Express status reporting that is required by the PCI Express spec.
PEGTXDEMPSEL - PEG Transmit De-Emphasis Select
Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
63:60
59:48
47:44
43:32
31:28
27:16
15:12
11:0
Bit
Bit
31
Access
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Default
Value
Value
000h
000h
000h
FFFh
0h
0h
0h
0h
0b
Reserved
Next Transmit Sequence Number (NTSN)
Value of the NXT_TRANS_SEQ counter. This counter
represents the transmit Sequence number to be applied
to the next TLP to be transmitted onto the Link for the
first time.
Reserved
Next Packet Sequence Number (NPSN)
Packet sequence number to be applied to the next TLP to
be transmitted or re-transmitted onto the Link.
Reserved
Next Receive Sequence Number (NRSN)
This is the sequence number associated with the TLP
that is expected to be received next.
Reserved
Last Acknowledged Sequence Number (LASN)
This is the sequence number associated with the last
acknowledged TLP.
0/1/0/MMR
218-21Fh
0000000000000FFFh
64 bits
0/1/0/MMR
DA8-DABh
43E00BF9h
32 bits
Reserved
RO
RW; RO
(Sheet 1 of 4)
Processor Configuration Registers
Description
Description
Datasheet