CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 159

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.10
1.13.11
Datasheet
SBUSN1 - Secondary Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies the bus number assigned to the second bus side of the “virtual”
bridge, i.e., to PCI Express-G. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
SUBUSN1 - Subordinate Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express-G. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express-G.
7:0
Bit
7:0
Bit
Access
Access
RW
RW
Default
Default
Value
Value
00h
00h
Subordinate Bus Number (BUSN)
This register is programmed by configuration software with
the number of the highest subordinate bus that lies behind
the Device 1 bridge. When only a single PCI device resides on
the PCI Express-G segment, this register will contain the
same value as the SBUSN1 register.
Secondary Bus Number (BUSN)
This field is programmed by configuration software with the
bus number assigned to PCI Express-G.
0/1/0/PCI
19h
00h
RW
8 bits
0/1/0/PCI
1Ah
00h
RW
8 bits
Description
Description
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