CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 58
CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
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1.8.14
58
GGC - Processor Graphics Control Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
All the bits in this register are Intel TXT lockable.
15:12
Bit
Bit
0
Access
Access
RW-L
RO
Default
Default
Value
Value
0h
0b
Reserved
MCHBAR Enable (MCHBAREN)
0 = MCHBAR is disabled and does not claim any memory
1 = MCHBAR memory mapped accesses are claimed and
This register is locked by Intel TXT.
Encoding
0/0/0/PCI
52-53h
0030h
RW-L; RO
16 bits
decoded appropriately
(Sheet 2 of 2)
(Sheet 1 of 4)
0b
1b
MCHBAR is disabled
MCHBAR is enabled
Processor Configuration Registers
Description
Description
Description
Datasheet
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