CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 51

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.8.4
Datasheet
PCISTS - PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This status register reports the occurrence of error events on Device 0's PCI interface.
Since the processor Device 0 does not physically reside on PCI_A many of the bits are
not implemented.
10:9
Bit
15
14
13
12
11
8
Access
RWC
RWC
RWC
RWC
RWC
RO
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
Detected Parity Error (DPE)
This bit is set when this Device receives a Poisoned TLP.
Signaled System Error (SSE)
This bit is set to 1 when the processor Device 0 generates
an SERR message over DMI for any enabled Device 0 error
condition. Device 0 error conditions are enabled in the
PCICMD, ERRCMD, and DMIUEMSK registers. Device 0
error flags are read/reset from the PCISTS, ERRSTS, or
DMIUEST registers. Software clears this bit by writing a 1
to it.
Received Master Abort Status (RMAS)
This bit is set when the processor generates a DMI request
that receives an Unsupported Request completion packet.
Software clears this bit by writing a 1 to it.
Received Target Abort Status (RTAS)
This bit is set when the processor generates a DMI request
that receives a Completer Abort completion packet.
Software clears this bit by writing a 1 to it.
Signaled Target Abort Status (STAS)
The processor will not generate a Target Abort DMI
completion packet or Special Cycle. This bit is not
implemented in the processor and is hard wired to a 0.
Writes to this bit position have no effect.
DEVSEL Timing (DEVT)
These bits are hard wired to “00”. Writes to these bit
positions have no affect. Device 0 does not physically
connect to PCI_A. These bits are set to “00” (fast decode)
so that optimum DEVSEL timing for PCI_A is not limited by
the processor.
Master Data Parity Error Detected (DPD)
This bit is set when DMI received a Poisoned completion
from PCH.
This bit can only be set when the Parity Error Enable bit in
the PCI Command register is set.
0/0/0/PCI
6-7h
0090h
RWC; RO
16 bits
(Sheet 1 of 2)
Description
51