CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 134

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.10.18
134
MTDPCCRWTWHOTTH - Memory TDP Controller Combined
RD/WR Thermal Weight Hot Thresholds
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The settings in these registers apply to the combined memory Rd/Wr thermal weight
trackers in both ch0 and ch1.
The range of threshold supported allows sub-millisecond differentiation among the
thresholds. For example,
31:16
Bit
let MEMCRWTWHOTTH[38:23]=0007h and MEMCRWTWHOTM1TH[38:23]=0006h;
let TW counter operational clock frequency be 333 MHz mb4clk=3 ns period;
let TW value[7:0]= FFh;
Elapsed time to cross these 2 thresholds = (2^23 / 2^8) * 3 ns = 98,304 ns =
0.098 ms.
Access
RW
Default
0000h
Value
Memory Combined Rd/Wr Thermal Weight Hot
Threshold (MemCRWTWHotTh)
The hot thermal weight threshold used for memory
combined Rd/Wr thermal weight tracking. This 16-bit value
is compared to the MSB (i.e., [38:23]) of the thermal weight
counter value, to determine whether the HOT thermal
weight threshold is reached or not.
Since there are 8 NearHot-to-Hot levels defined, the
minimum that this field should be set to i0008h, to avoid
overlapping levels if all 8 NearHot-to-Hot thresholds are to
be used. Overlapping levels can certainly be set when less
than 8 thresholds are to be used. To use 1 threshold setting
only, effectively disabling adaptive throttling, all 8 thresholds
can be set to the same value.
0/0/0/MCHBAR
2F0-2F3h
00000000h
RW
32 bits
(Sheet 1 of 2)
Processor Configuration Registers
Description
Datasheet