CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 35

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.2.6
Datasheet
Note that the GMCH memory range registers described above are used to allocate
memory address space for any PCI Express devices sitting on PCI Express that require
such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In
other words, the memory access enable bit must be set to enable the memory base/
limit and pre-fetchable base/limit windows.
For the processor, the upper PMUBASE/PMULIMIT registers have been implemented for
PCI Express Spec compliance. The processor locates MMIO space above 4 GB using
these registers.
Graphics Memory Address Ranges
The GMCH can be programmed to direct memory accesses to IGD when addresses are
within any of five ranges specified via registers in GMCH Device 2 configuration space.
These ranges can reside above the Top-of-Low-DRAM and below high BIOS and APIC
address ranges. They MUST reside above the top of memory (TOLUD) and below 4 GB
so they do not steal any physical DRAM memory space.
Alternatively, these ranges can reside above 4 GB, similar to other BARs which are
larger than 32 bits in size.
GMADR is a Prefetchable range in order to apply USWC attribute (from the processor
point of view) to that range. The USWC attribute is used by the processor for write
combining.
1. The Graphics Memory Aperture Base Register (GMADR) is used to access graphics
2. The Graphics Translation Table Base Register (GTTADR) is used to access the
memory allocated via the graphics translation table.
translation table and graphics control registers. This is part of GTTMMADR register.
35