CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 67

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.8.20
Datasheet
TOM - Top of Memory
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This Register contains the size of physical memory. BIOS determines the memory size
reported to the OS using this Register.
15:10
9:0
Bit
Access
RW-L
RO
Default
Value
001h
00h
Reserved
Top of Memory (TOM)
This register reflects the total amount of populated physical
memory. This is NOT necessarily the highest main memory
address (holes may exist in main memory address map due
to addresses allocated for memory mapped IO). These bits
correspond to address Bits 35:26 (64-MB granularity). Bits
25:0 are assumed to be 0. All the bits in this register are
locked in Intel VT-d mode.
MCH determines the base of EP stolen memory by
subtracting the EP stolen memory size from TOM.
0/0/0/PCI
A0-A1h
0001h
RO; RW-L
16 bits
Description
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