CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 258

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.18.3
258
ECAP_REG - Extended Capability Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to report DMA-remapping hardware extended capabilities.
63:32
Bit
2:0
Bit
4
3
Access
Access
RO
RO
RO
RO
00000000h Reserved
Default
Value
Default
010b
Value
1b
0b
Required Write-Buffer Flushing (RWBF)
0 = Indicates no write-buffer flushing needed to ensure
1 = Indicates software must explicitly flush the write buffers
Advanced Fault Logging (AFL)
0 = Indicates advanced fault logging not supported. Only
1 = Indicates advanced fault logging is supported.
Number of Domains Supported (ND)
000b: Hardware supports 4-bit domain-ids with support for up
to 16 domains.
001b: Hardware supports 6-bit domain-ids with support for up
to 64 domains.
010b: Hardware supports 8-bit domain-ids with support for up
to 256 domains.
011b: Hardware supports 10-bit domain-ids with support for
up to 1024 domains.
100b: Hardware supports 12-bit domain-ids with support for
up to 4-K domains.
101b: Hardware supports 14-bit domain-ids with support for
up to 16-K domains.
110b: Hardware supports 16-bit domain-ids with support for
up to 64-K domains.
111b: Reserved.
changes to memory-resident structures are visible to
hardware.
(through the Global Command register) to ensure updates
made to memory-resident DMA-remapping structures are
visible to hardware. Refer Section 9.1 for more details on
write buffer flushing requirements.
primary fault logging is supported.
0/0/0/VC0PREMAP
10-17h
0000000000001000h
RO
64 bits
(Sheet 4 of 4)
(Sheet 1 of 3)
Description
Processor Configuration Registers
Description
Datasheet