CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 286

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.18.24
1.18.25
286
IEDATA_REG - Invalidation Event Data Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the Invalidation Event interrupt message data. This register is
treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
IEADDR_REG - Invalidation Event Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the Invalidation Event Interrupt message address. This register is
treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
31:16
31:2
15:0
1:0
Bit
Bit
Access
Access
RW
RW
RW
RO
00000000h
Default
Default
0000h
0000h
Value
Value
00b
Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit
interrupt data fields.
Hardware implementations supporting only 16-bit interrupt
data treat this field as RSVD.
Interrupt Message Data (IMD)
Data value in the interrupt request.
Message Address (MA)
When fault events are enabled, the contents of this register
specify the DWORD-aligned address (Bits 31:2) for the
interrupt request.
Reserved
0/0/0/VC0PREMAP
A4-A7h
00000000h
RW
32 bits
0/0/0/VC0PREMAP
A8-ABh
00000000h
RO; RW
32 bits
Processor Configuration Registers
Description
Description
Datasheet