CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 343

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
Bit
3
2
1
0
Access
RW-L
RW-L
RW-L
RW-L
Default
Value
0b
0b
0b
0b
DMI VC1 Hit Queue Throttling (DMIVC1HTQT)
0 = No throttling at the outlet of the DMI VC1 Hit Queue.
1 = Throttle the outlet DMI VC1 Hit Queue to fill up the
DMIVC1 TLB Disable (DMIVC1TLBDIS)
0 = Normal mode, DMIVC1 TLBs are enabled and normal hit/
1 = DMIVC1 TLBs are disabled and each GPA request will
Global IOTLB Invalidation Promotion (GLBIOTLBINV)
This bit controls the IOTLB Invalidation behavior of the DMA
remap engine.
0 = Normal operation.
1 = Any type of IOTLB Invalidation (valid or invalid) is
Global Context Invalidation Promotion (GLBCTXTINV)
This bit controls the Context Invalidation behavior of the
DMA remap engine.
0 = Normal operation.
1 = Any type of Context Invalidation (valid or invalid) is
queue.
miss flows are followed.
result in a miss and a root walk is requested from Intel
VT-d Dispatcher.
promoted to Global IOTLB Invalidation.
promoted to Global Context Invalidation.
(Sheet 2 of 2)
Description
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