CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 326

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.19.15
326
PLMBASE_REG - Protected Low-Memory Base Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to set up the base address of DMA-protected low-memory region below 4 GB.
This register must be set up before enabling protected memory through PMEN_REG,
and must not be updated when protected memory regions are enabled.
This register is treated as RO for implementations not supporting protected low
memory region (PLMR field reported as Clear in the Capability register).
The alignment of the protected low memory region base depends on the number of
reserved bits (N:0) of this register. Software may determine N by writing all 1s to this
register, and finding the most significant bit position with 0 in the value read back from
the register. Bits N:0 of this register are decoded by hardware as all 0’s.
Software must setup the protected low memory region below 4 GB. Intel VT-d
specification Section 10.4.18 describes the Protected Low-Memory Limit register and
hardware decoding of these registers.
Software must not modify this register when protected memory regions are enabled.
(PRS field Set in PMEN_REG).
31:21
20:0
Bit
Access
RW
RO
000000h
Default
Value
000h
Protected Low-Memory Base (PLMB)
This register specifies the base of protected low-memory
region in system memory.
Reserved
0/0/0/DMIVC1REMAP
68-6Bh
00000000h
RO; RW
32 bits
Processor Configuration Registers
Description
Datasheet