CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 188

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

188
9:4
Bit
14
13
12
11
10
Access
RWC
RO
RO
RO
RO
RO
Default
Value
00h
0b
0b
1b
0b
0b
Link Bandwidth Management Status (LBWMS)
This bit is set to 1b by hardware to indicate that either of the
following has occurred without the port transitioning through
DL_Down status: A link retraining initiated by a write of 1b to
the Retrain Link bit has completed.
Note: This bit is Set following any write of 1b to the Retrain
Link bit, including when the Link is in the process of retraining
for some other reason.
Hardware has autonomously changed link speed or width to
attempt to correct unreliable link operation, either through an
LTSSM timeout or a higher level process
This bit must be set if the Physical Layer reports a speed or
width change was initiated by the downstream component
that was not indicated as an autonomous change.
Data Link Layer Link Active (Optional) (DLLLA)
This bit indicates the status of the Data Link Control and
Management State Machine. It returns a 1b to indicate the
DL_Active state, 0b otherwise. This bit must be implemented
if the corresponding Data Link Layer Active Capability bit is
implemented. Otherwise, this bit must be hard wired to 0b.
Slot Clock Configuration (SCC)
0 = The device uses an independent clock irrespective of the
1 = The device uses the same physical reference clock that
Link Training (LTRN)
Indicates that the Physical Layer LTSSM is in the
Configuration or Recovery state, or that 1b was written to the
Retrain Link bit but Link training has not yet begun. Hardware
clears this bit when the LTSSM exits the Configuration/
Recovery state once Link training is complete.
Undefined (Undefined)
The value read from this bit is undefined. In previous versions
of this specification, this bit was used to indicate a Link
Training Error. System software must ignore the value read
from this bit. System software is permitted to write any value
to this bit.
Negotiated Link Width (NLW)
Indicates negotiated link width. This field is valid only when
the link is in the L0, L0s, or L1 states (after link width
negotiation is successfully completed).
00h: Reserved
01h: X1
02h: X2
04h: X4
08h: X8
10h: X16
All other encodings are reserved.
presence of a reference on the connector.
the platform provides on the connector.
Description
Processor Configuration Registers
Datasheet