CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 251

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.17.1
1.17.2
Datasheet
Note:
Index - MMIO Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
MMIO_INDEX: A 32 bit IO write to this port loads the offset of the MMIO register or
offset into the GTT that needs to be accessed. An IO Read returns the current value of
this register. An 8-/16-bit IO write to this register is completed by the processor but
does not update this register.
This mechanism to access internal graphics MMIO registers must not be used to access
VGA IO registers which are mapped through the MMIO space. VGA registers must be
accessed directly through the dedicated VGA IO ports.
Data - MMIO Data Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
MMIO_DATA: A 32-bit IO write to this port is re-directed to the MMIO register/GTT
location pointed to by the MMIO-index register. A 32-bit IO read to this port is re-
directed to the MMIO register address pointed to by the MMIO-index register regardless
of the target selection in MMIO_INDEX(1:0). 8- or 16-bit IO writes are completed by
the processor and may have un-intended side effects, hence must not be used to
access the data port. 8- or 16-bit IO reads are completed normally.
If the target field in MMIO Index selects “GTT”, reads to MMIO data return is undefined.
31:0
31:2
Bit
1:0
Bit
Access
Access
RW
RW
RW
00000000h
Default
Value
00000000h
Default
Value
00b
MMIO Data Window (DATA)
0/2/0/PCI IO
0-3h
00000000h
RW
32 bits
0/2/0/PCI IO
4-7h
00000000h
RW
32 bits
Register/GTT Offset (REGGTTO)
This field selects any one of the DWORD registers within
the MMIO register space of Device 2 if the target is
MMIO Registers.
This field selects a GTT offset if the target is the GTT.
Target (TARG)
00: MMIO Registers
01: GTT
1X: Reserved
Description
Description
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