CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 274

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CP80617004119AES LBU3

Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet

Specifications of CP80617004119AES LBU3

Lead Free Status / RoHS Status
Compliant
274
29:0
Bit
30
Access
RO
RO
00000000h
Default
Value
0h
Interrupt Pending (IP)
Hardware sets the IP field whenever it detects an interrupt
condition. Interrupt condition is defined as: - When primary
fault logging is active, an interrupt condition occurs when
hardware records a fault through one of the Fault Recording
registers and sets the PPF field in Fault Status register. If
the PPF field was already set at the time of recording a
fault, it is not treated as a new interrupt condition.
When advanced fault logging is active, an interrupt
condition occurs when hardware records a fault in the first
fault record (at index 0) of the current fault log and sets the
APF field in the Advanced Fault Log register. If the APF field
was already set at the time of detecting/recording a fault, it
is not treated as a new interrupt condition.
The IP field is kept set by hardware while the interrupt
message is held pending. The interrupt message could be
held pending due to interrupt mask (IM field) being set, or
due to other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt
message pending condition is serviced. This could be due to
either
(a) Hardware issuing the interrupt message due to either
change in the transient hardware condition that caused
interrupt message to be held pending or due to software
clearing the IM field.
(b) Software servicing the interrupting condition through
one of the following ways:
Reserved
• When primary fault logging is active, software clearing
• When advanced fault logging is active, software clearing
the Fault (F) field in all the Fault Recording registers
with faults, causing the PPF field in Fault Status register
to be evaluated as clear.
the APF field in Advanced Fault Log register.
(Sheet 2 of 2)
Processor Configuration Registers
Description
Datasheet

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