CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 199

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
9:7
Bit
6
5
4
Access
RW-S
RW-S
RW-S
RW
Default
Value
000b
0b
0b
0b
Transmit Margin (txmargin)
This field controls the value of the non-de-emphasized
voltage level at the Transmitter pins. This field is reset to
000b on entry to the LTSSM Polling.Configuration substate
(see Chapter 4 for details of how the transmitter voltage
level is determined in various states).
Encodings:
000: Normal operating range
001: 800-1200 mV for full swing and 400-700 mV for
half-swing
010 - (n-1) Values must be monotonic with a non-zero
slope. The value of n must be greater than 3 and less than
7. At least two of these must be below the normal
operating range 200-400 mV for full-swing and 100-200
mV for half-swing -
111: reserved
Default value is 000b.
Components that support only the 2.5GT/s speed are
permitted to hardwire this bit to 0b.
Selectable De-emphasis (selectabledeemphasis)
Encodings:
1b) -3.5dB
0b -6 dB
Default value is implementation specific, unless a specific
value is required for a selected form factor or platform.
When the Link is operating at 2.5GT/s speed, the setting
of this bit has no effect. Components that support only the
2.5GT/s speed are permitted to hardwire this bit to 0b.
Hardware Autonomous Speed Disable (HASD)
When set to 1b this bit disables hardware from changing
the link speed for reasons other than attempting to
correct unreliable link operation by reducing link speed.
Enter Compliance (EC)
Software is permitted to force a link to enter Compliance
mode at the speed indicated in the Target Link Speed field
by setting this bit to 1b in both components on a link and
then initiating a hot reset on the link.
(Sheet 2 of 3)
Description
199