CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 19

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.2.1.3
1.2.2
Datasheet
PAM (000C_0000h-000F_FFFFh)
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory
Area. Each section has Read enable and Write enable attributes. The CPU
documentation will now contain the registers and decode rules/restrictions.
The PAM registers have moved to the CPU. For the PAM register details, refer to CPU
documentation.
The CPU contains the PAM registers and the GMCH has no knowledge of the register
programming. The CPU decodes the request and routes to the appropriate destination
(DRAM or DMI) by sending the request on HOM or NCS/NCB.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM. Graphics translated requests to this region are not allowed. If such a mapping
error occurs, the request is routed to 000C_0000h. Writes will have the byte enables
de-asserted.
Main Memory Address Range (1 MB - TOLUD)
This address range extends from 1 MB to the top of Low Usable physical memory that is
permitted to be accessible by the GMCH (as programmed in the TOLUD register). The
CPU will route all addresses within this range as HOM accesses which is forwarded by
the GMCH to the DRAM unless it falls into the optional TSEG, optional ISA Hole, or
optional IGD stolen VGA memory.
•
•
•
ISA Expansion Area (000C_0000h-000D_FFFFh)
Extended System BIOS Area (000E_0000h-000E_FFFFh)
System BIOS Area (000F_0000h-000F_FFFFh)
19