CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 20

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.2.2.1
1.2.2.2
20
Figure 3.
Main Memory Address Range
ISA Hole (15 MB-16 MB)
This register moved to the CPU. As such, the CPU performs the necessary decode and
routes the request appropriately. Specifically, if no hole is created, the CPU will route
the request to DRAM (HOM channel). If a hole is created, the CPU will route the request
on NCS/NCB, since the request does not target DRAM.
Graphics translated requests to the range will always route to DRAM.
TSEG
The TSEG register moved from the GMCH to the CPU. The GMCH will have no direct
knowledge of the TSEG size. For CPU initiated transactions, the CPU will perform
necessary decode and route appropriately on HOM (to DRAM) or NCS/NCB.
TSEG is below IGD stolen memory, which is at the Top of Low Usable physical memory
(TOLUD). When SMM is enabled, the maximum amount of memory available to the
system is equal to the amount of physical DRAM minus the value in the TSEG register.
BIOS will calculate and program a register, so the GMCH has knowledge of where
(TOLUD)-(GFX stolen)-(GFX GTT stolen)-(TSEG) is located. This is indicated by the
TSEG_BASE register.
Contains:
Dev 0, 1, 2, 6, 7
BARS & ICH/PCI
ranges
FFFF_FFFFh
00F0_0000h
0100_0000h
0010_0000h
0h
DOS Compatibility Memory
PCI Memory Range
ISA Hole (optional)
Main Memory
Main Memory
FLASH
IGGTT
TSEG
APIC
DPR
IGD
LT
Processor Configuration Registers
TOLUD
TSEG_BASE
4GB Max
1MB
0MB
16MB
15MB
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