CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 328

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.19.17
328
PHMBASE_REG - Protected High-Memory Base Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to set up the base address of DMA-protected high-memory region. This
register must be set up before enabling protected memory through PMEN_REG, and
must not be updated when protected memory regions are enabled.
This register is always treated as RO for implementations not supporting protected high
memory region (PHMR field reported as Clear in the Capability register).
The alignment of the protected high memory region base depends on the number of
reserved bits (N:0) of this register. Software may determine N by writing all 1’s to this
register, and finding most significant zero bit position below host address width (HAW)
in the value read back from the register. Bits N:0 of this register are decoded by
hardware as all 0s.
Software may setup the protected high memory region either above or below 4 GB.
Intel VT-d specification Section 10.4.20 describes the Protected High-Memory Limit
register and hardware decoding of these registers.
Software must not modify this register when protected memory regions are enabled.
(PRS field Set in PMEN_REG).
63:21
20:0
Bit
Access
RW
RO
00000000
000000h
Default
Value
000h
Protected High-Memory Base (PHMB)
This register specifies the base of protected (high) memory
region in system memory.
Hardware ignores, and does not implement, Bits 63:HAW,
where HAW is the host address width.
Reserved
0/0/0/DMIVC1REMAP
70-77h
0000000000000000h
RO; RW
64 bits
Processor Configuration Registers
Description
Datasheet