CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 217

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.15.8
Datasheet
DMIVC1RCAP - DMI VC1 Resource Capability
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:24
22:16
14:8
7:0
Bit
23
15
Access
RO
RO
RO
RO
RO
RO
Default
Value
00h
00h
00h
01h
0b
1b
Reserved for Port Arbitration Table Offset (RSVD)
Reserved
Reserved for Maximum Time Slots (RSVD)
Reject Snoop Transactions (REJSNPT)
0 = Transactions with or without the No Snoop bit set within
1 = When Set, any transaction for which the No Snoop
Reserved
Port Arbitration Capability (PAC)
Having only Bit 0 set indicates that the only supported
arbitration scheme for this VC is non-configurable hardware-
fixed.
0/0/0/DMIBAR
1C-1Fh
00008001h
RO
32 bits
the TLP header are allowed on this VC.
attribute is applicable but is not set within the TLP
Header is rejected as an Unsupported Request.
Description
217