CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 63

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.8.16
Datasheet
DMIBAR - Root Complex Register Range Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the processor. There is no physical memory within this 4-KB window
that can be addressed. The 4-KB reserved by this register does not alias to any PCI
3.0-compliant memory mapped space. On reset, the Root Complex configuration space
is disabled and must be enabled by writing a 1 to DMIBAREN [Device 0, Offset 68h,
Bit 0] All the bits in this register are locked in Intel TXT mode.
63:36
35:12
11:1
Bit
0
Access
RW-L
RW-L
RO
RO
0000000h
000000h
Default
Value
000h
0b
Reserved (DMIBAR_rsv)
DMI Base Address (DMIBAR)
This field corresponds to Bits 35:12 of the base address DMI
configuration space. BIOS will program this register resulting
in a base address for a 4-KB block of contiguous memory
address space. This register ensures that a naturally aligned
4-KB space is allocated within the first 64 GB of addressable
memory space. System Software uses this base address to
program the DMI register set. All the bits in this register are
locked in Intel VT-d mode.
Reserved
DMIBAR Enable (DMIBAREN)
0 = DMIBAR is disabled and does not claim any memory
1 = DMIBAR memory mapped accesses are claimed and
This register is locked by Intel VT-d.
Encoding
decoded appropriately
0/0/0/PCI
68-6Fh
0000000000000000h
RW-L; RO
64 bits
0b
1b
DMIBAR disabled
DMIBAR enabled
Description
Description
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