CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 214

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.15.4
1.15.5
214
DMIPVCCTL - DMI Port VC Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
DMIVC0RCAP - DMI VC0 Resource Capability
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:24
22:16
14:8
15:4
7:0
3:1
Bit
Bit
23
15
0
Access
Access
RW
RO
RO
RO
RO
RO
RO
RO
RO
Default
Default
Value
Value
000h
000b
00h
00h
00h
01h
0b
0b
0b
Reserved for Port Arbitration Table Offset (RSVD)
Reserved
Reserved for Maximum Time Slots (RSVD)
Reject Snoop Transactions (REJSNPT)
0 = Transactions with or without the No Snoop bit set within
1 = Any transaction for which the No Snoop attribute is
Reserved
Port Arbitration Capability (PAC)
Having only Bit 0 set indicates that the only supported
arbitration scheme for this VC is non-configurable hardware-
fixed.
Reserved
VC Arbitration Select (VCAS)
This field is programmed by software to the only possible
value as indicated in the VC Arbitration Capability field.
The value 000b when written to this field will indicate the VC
arbitration scheme is hardware fixed (in the root complex).
This field cannot be modified when more than one VC in the
LPVC group is enabled.
Robin
See the PCI Express Base Specification for more details.
Reserved for Load VC Arbitration Table (RSVD)
000:Hardware fixed arbitration scheme, e.g., Round
Others:Reserved
0/0/0/DMIBAR
C-Dh
0000h
RO; RW
16 bits
0/0/0/DMIBAR
10-13h
00000001h
RO
32 bits
the TLP header are allowed on this VC.
applicable but is not set within the TLP Header is
rejected as an Unsupported Request.
Processor Configuration Registers
Description
Description
Datasheet