CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 305

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
12:8
Bit
7
6
5
4
Access
RO
RO
RO
RO
RO
Default
Value
02h
0b
1b
1b
1b
Supported Adjusted Guest Address Widths (SAGAW)
This 5-bit field indicates the supported adjusted guest
address widths (which in turn represents the levels of page-
table walks for the 4-KB page size) supported by the
hardware implementation.
A value of 1 in any of these bits indicates the corresponding
adjusted guest address width is supported. The adjusted
guest address widths corresponding to various bit positions
within this field are:
Software must ensure that the adjusted guest address width
used to setup the page tables is one of the supported guest
address widths reported in this field.
Caching Mode (CM)
0 = Hardware does not cache not present and erroneous
1 = Hardware may cache not present and erroneous
Refer to VT-d specification Section 6.1 for more details on
caching mode.
Hardware implementations are required to support
operation corresponding to CM=0.
Protected High-Memory Region (PHMR)
0 = Indicates protected high-memory region not supported.
1 = Indicates protected high-memory region is supported.
Protected Low-Memory Region (PLMR)
0 = Indicates protected low-memory region not supported.
1 = Indicates protected low-memory region is supported.
Required Write-Buffer Flushing (RWBF)
0 = Indicates no write-buffer flushing needed to ensure
1 = Indicates software must explicitly flush the write buffers
0: 30-bit AGAW (2-level page table)
1: 39-bit AGAW (3-level page table)
2: 48-bit AGAW (4-level page table)
3: 57-bit AGAW (5-level page table)
4: 64-bit AGAW (6-level page table)
entries in any of the remapping caches. Invalidations
are not required for modifications to individual not
present or invalid entries. However, any modifications
that result in decreasing the effective permissions or
partial permission increases require invalidations for
them to be effective.
mappings in the remapping caches. Any software
updates to the DMA-remapping structures (including
updates to not-present or erroneous entries) require
explicit invalidation.
changes to memory-resident structures are visible to
hardware.
to ensure updates made to memory-resident DMA-
remapping structures are visible to hardware. Refer VT-
d specification Section 11.1 for more details on write
buffer flushing requirements.
(Sheet 4 of 5)
Description
305