CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 200

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.47
200
LSTS2 - Link Status 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
15:1
3:0
Bit
Bit
0
Access
Access
RW
RO
RO
Default
Value
Default
0000h
Value
2h
0b
Target Link Speed (TLS)
link operational speed by restricting the values advertised
by the upstream component in its training sequences.
Defined encodings are:
0001b 2.5Gb/s Target Link Speed
All other encodings are reserved.
If a value is written to this field that does not correspond
to a speed included in the Supported Link Speeds field,
the result is undefined. The default value of this field is
the highest link speed supported by the component (as
reported in the Supported Link Speeds field of the Link
Capabilities Register) unless the corresponding platform /
form factor requires a different default value. For both
Upstream and Downstream ports, this field is used to set
the target compliance mode speed when software is using
the Enter Compliance bit to force a link into compliance
mode.
For Downstream ports, this field sets an upper limit on
0/1/0/PCI
D2-D3h
0000h
16 bits
Reserved
Current De-emphasis Level (CURDELVL)
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s speed, this bit is
0b.
RO
(Sheet 3 of 3)
Current De-emphasis Level –
Processor Configuration Registers
Description
Description
Datasheet