TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 191

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EBC
9.1.
External Bus Interface supports NOR-Flash interface (as boot device), NAND-Flash control, and two kinds of ASIC I/O
interfaces. In terms of bus width, 8/16 bus width are available. Figure 9-1 shows typical configuration with 8/16-bit bus
mode.
9.1.1.
Figure 9-1 below shows an example of NOR-Flash, NAND-Flash, and ASIC connectivity on the External bus.
Rev. 3.1 November 1, 2005
CPU RESET*
Note: If ISA mode is enable then DMAREQ[2] and DMAACK[2] are dedicated for ISA interface.
Address Latch
Basic Structure
External Bus Connection Diagram
Otherwise if ISA mode is not used then DMAREQ[2] and DMAACK[2] can be used for DMA transfer.
Address Latch
TC58FVM6T2AFT65 : 8MB (X16)
Figure 9-1 External Circuit for External Bus Interface for 8/16-bit mode.
NOR Flash
TX4939 External Bus Port
Chapter 9. External Bus Interface
9-1
A5
A4
A3
A2
A1
A0
EN
D5
D4
D3
D2
D1
D0
Q5
Q4
Q3
Q2
Q1
Q0
TC58NVG1S8BFT100: 256MB
TC58DVM82F1FT00: 32MB
NAND Flash
DMAACK[2]
DMAREQ[2]
CE3*
Another NAND
Toshiba RISC Processor
BE[0]
BE[1]
ACK*/READY
INT2*
DMADONE*
INT2*
INT1*
INT0*
CE3*
CE2*
CE1*
DMAACK[2]
DMAREQ[2]
DMAACK[1]
DMAREQ[1]
DMAACK[0]
DMAREQ[0]
SYSCLK
BE[1]
BE[0]
SWE*
OE*
ACK*
SADB[15:8]
SADB[7:0]
SA[5:0]
SADB[15:8]
SADB[7:0]
SA[22:15]
SA[14:7]
SA[6:1]
SA[0]*
BHE*
CS*
IOW*
IOR*
WAIT
IREQ*
TX4939
Rev 2.22
9
9