TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 479

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
The device recognition sequence is a process that detects any devices connected to the ATA Bus and fetches information on
those devices.
Rev. 3.1 November 1, 2005
(6)
(7)
(8)-1
(8)-2
(9)
(10)
(11)-1
(11)-2
Execute the device recognition sequence. (See below for details.)
Use the ATA Shadow Register to set commands or parameters such as the LBA value.
For read commands: Wait for an interrupt from the device, read the Status Register of the ATA
Shadow Register, then confirm that the DRQ bit is set. (If the DRQ bit has not been set yet, wait
until it is set.)
For write commands: Read the Status Register of the ATA Shadow Register immediately after a
command is issued. Confirm that the DRQ bit is set. (If the DRQ bit has not been set yet, wait until
it is set.)
Set bit [0] (START_STOPBM) of the DMA Command Register, then start data transfer.
Wait for an interrupt from the device or transfer end interrupt.
For read commands: Acknowledge that transfer has ended if a transfer end interrupt is issued.
Then, shift to the next process. If there is an interrupt from the device, then read the Status
Register of the ATA Shadow Register, acknowledge that the DRQ bit is set (in this case, this
controller is also in the interrupt status that is indicated at bit [6](Reach Multiple INT) of the
Interrupt Control Register), set bit [3] and bit [2] of the System Control Register, start transfer of the
next sector and return to process (10).
For write commands: Acknowledge an interrupt from the device. If a transfer end interrupt is
inserted simultaneous to an interrupt from the device, then read the Status Register of the ATA
Shadow Register, confirm that the transfer has ended, then transition to the next process. If no
transfer end interrupt was issued, confirm that the DRQ bit is set (in this case, this controller is also
in the interrupt status that is indicated at bit [6](Reach Multiple INT) of the Interrupt Control
Register), set bit [3] and bit [2] of the System Control Register, start transfer of the next sector, then
return to process (10).
17-25
Toshiba RISC Processor
TX4939
17
17