TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 654

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ACLINK
24.3.6.2. DMA Operation
When ACLC’s REQ latch (refer to Figure 24-7 and Figure 24-8) needs to read or write sample-data, it issues a DMA
request.
ACLC deasserts the request.
points to the corresponding sample-data register for the DMA channel.
Setup the DMA Channel Control Registers (DMCCRn) in DMAC as follows.
Note: Use this setting when DMA chain operation is utilized
For a transmission channel, assign the address of ACLC Audio PCM Output/Surround/Center/LFE/Modem Output
Register (ACAUDO/SURR/CENT/LFE/MODODAT) to the DMAC destination address register (DMDARn).
reception channel, assign the address of ACLC Audio input/Modem Input Register (ACAUDI/MODIDAT) to the DMAC
source address register (DMSARn).
When any DMA request is pending, the REQ latch will not deasserted the request until the corresponding sample-data
register is accessed.
corresponding to the DMA will not clear the REQ latch.
The procedure to continuously push or pull the sample-data stream through the chain DMA operation follows the DMAC
specification.
Rev. 3.1 November 1, 2005
When DMAC acknowledges the request by performing write- or read-access to the ACLC sample-data register,
Immediate chain
DMA request polarity
DMA acknowledge polarity
Request sense
Sample chain
Transfer size
Transfer address mode
Refer to section 8.3.10 for this respect.
Just unsetting ACLC Control Enable Register (ACCTLEN)’s DMA Enable (xxxxDMA) bit
Therefore, the software must properly set up DMAC so that the source or destination
Enable
Low-active
Low-active
Level-sensitive
1 word
1 word
Dual
24-12
DMCCRn.IMMCHN = 1 [Note]
DMCCRn.REQPOL = 0
DMCCRn.ACKPOL = 0
DMCCRn.EGREQ = 0
DMCCRn.SMPCHN = 1
DMCCRn.XFSZ = 010b
DMCCRn.SNGAD = 0
Toshiba RISC Processor
For a
TX4939
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