TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 360

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Toshiba RISC Processor
DDR
TX4939
15.11. Read Data Capture
The read data capture logic is responsible for capturing the dq outputs from the DRAM devices with the delayed version of
dqs strobe signals from the DRAM devices and then passing the data back to the system clock domain. The dqs strobes
are first sent through the delay lines to ensure that the rising and falling edges of the strobes are in the middle of the valid
window of data.
DDR DRAM devices send a dqs strobe signal coincident with the read data so that the read data can be reliably captured by
a controller. The edges of this strobe are aligned with the data by the DRAM device. Both the rising and falling edges of
this strobe are used to capture data. It is assumed that the wires for the data and the associated dqs signals are routed with
the same length between the capture logic and the DRAM device. This will cause the rising and falling edges of the dqs
strobe to arrive at the capture logic at the same time the data is in transition. The raw dqs signal cannot be used as a clock
to a flip-flop to register the data since the data is not stable at the time the dqs edges are rising and falling.
A delayed version of the dqs signal must be used to capture the data. The amount of delay added to the dqs signals should
be calculated such that it gives the maximum margin to capture the read data. This calculated value is best described as
a relative number based on the period of the system clock since the frequency of the dqs signal is matched to the system
clock by the DRAMs. In the case shown in Figure 15-10 below, the delay is set to approximately 25% of the system clock.
The DLL will keep this relative delay constant so the read data from the DRAMs can be reliably captured.
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Figure 15-10 dqs Read Timing
The amount of delay introduced to the read dqs signal from DRAM is controlled by the TC300C_dll_dqs_delay_x and
TC300C_dll_dqs_sub_x parameters. Where x can have a value of 0, 1, 2 and 3 corresponding to each of the 4 DQ bytes.
Once the data from the DRAMs are registered in with the delayed dqs signal, the output of these registers must be
transferred to registers that are clocked by the main controller clock.
Rev. 3.1 November 1, 2005
15-30