TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 9

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
CHAPTER 13. TIMER/COUNTER CONTROLLER ....................................................................................................... 13-1
CHAPTER 14. DMA CONTROLLER............................................................................................................................. 14-1
CHAPTER 15. DDR SDRAM CONTROLLER ............................................................................................................... 15-1
Rev. 3.1 November 1, 2005
13.1. F
13.2. B
13.3. D
13.4. P
13.5. W
13.6. R
14.1. F
14.2. B
14.3. D
14.4. DMA C
14.5. T
15.1. F
15.2. R
15.3. DDR SDRAM I
15.4. R
15.5. P
15.6. P
13.3.1. Overview .................................................................................................................................................... 13-4
13.3.2. Counter Clock ............................................................................................................................................ 13-4
13.3.3. Counter ...................................................................................................................................................... 13-5
13.3.4. Interval Timer Mode ................................................................................................................................... 13-5
13.6.1. Timer Control Register n (TMTCRn) .........................................................................................................13-11
13.6.2. Timer Interrupt Status Register n (TMTISRn)........................................................................................... 13-12
13.6.3. Compare Register An (TMCPRAn) .......................................................................................................... 13-14
13.6.4. Compare Register Bn (TMCPRBn) .......................................................................................................... 13-15
13.6.5. Interval Timer Mode Register n (TMITMRn)............................................................................................. 13-16
13.6.6. Divide Register n (TMCCDRn)................................................................................................................. 13-17
13.6.7. Pulse Generator Mode Register n (TMPGMRn) ...................................................................................... 13-18
13.6.8. Watchdog Timer Mode Register n (TMWTMRn) ...................................................................................... 13-19
13.6.9. Timer Read Register n (TMTRRn) ........................................................................................................... 13-20
14.3.1. Transfer Mode ............................................................................................................................................ 14-4
14.3.2. On-chip Registers ...................................................................................................................................... 14-4
14.3.3. External I/O DMA Transfer Mode ............................................................................................................... 14-5
14.3.4. Internal I/O DMA Transfer Mode................................................................................................................. 14-6
14.3.5. Memory-Memory Copy Mode..................................................................................................................... 14-7
14.3.6. Memory Fill Transfer Mode......................................................................................................................... 14-7
14.3.7. Single Address Transfer ............................................................................................................................. 14-8
14.3.8. Dual Address Transfer.............................................................................................................................. 14-10
14.3.9. DMA Transfer ........................................................................................................................................... 14-14
14.3.10. Chain DMA Transfer............................................................................................................................... 14-15
14.3.11. Dynamic Chain Operation ...................................................................................................................... 14-17
14.3.12. Interrupts ................................................................................................................................................ 14-17
14.3.13. Transfer Stall Detection Function ........................................................................................................... 14-18
14.3.14. Arbitration Among DMA Channels.......................................................................................................... 14-18
14.3.15. Restrictions in Access to PCI Bus .......................................................................................................... 14-19
14.4.1. DMA Master Control Register (DM0MCR, DM1MCR).............................................................................. 14-22
14.4.2. DMA Channel Control Register (DM0CCRn, DM1CCRn) ........................................................................ 14-24
14.4.3. DMA Channel Status Register (DM0CSRn, DM1CSRn)) ......................................................................... 14-28
14.4.4. DMA Source Address Register (DM0SARn, DM1SARn) ......................................................................... 14-30
14.4.5. DMA Destination Address Register (DM0DARn, DM1DARn)................................................................... 14-31
14.4.6. DMA Chain Address Register (DM0CHARn, DM1CHARn) ...................................................................... 14-32
14.4.7. DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn)....................................................... 14-33
14.4.8. DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn)................................................ 14-34
14.4.9. DMA Count Register (DM0CNTRn, DM1CNTRn) .................................................................................... 14-35
14.4.10. DMA Memory Fiill Data Register (DM0MFDR, DM1MFDR) ................................................................... 14-36
14.5.1. External I/O Device – SRAM Dual Address Transfer................................................................................ 14-37
14.5.2. External I/O Device – SRAM Dual Address Transfer................................................................................ 14-39
14.5.3. External I/O Device (Non-burst) – Memory Dual Address Transfer .......................................................... 14-40
15.3.1. Pin Signals ................................................................................................................................................. 15-3
15.4.1. Write........................................................................................................................................................... 15-6
EATURES
EATURES
IMING
EATURES
LOCK
ULSE
LOCK
RECHARGE
OWER
ETAILED
EGISTERS
ETAILED
EGISTER
EAD
ATCHDOG
.................................................................................................................................................................. 15-4
G
D
D
ONTROLLER
D
-D
ENERATOR
IAGRAM
IAGRAM
IAGRAMS
E
E
OWN
........................................................................................................................................................... 13-1
........................................................................................................................................................... 14-1
........................................................................................................................................................... 15-1
M
XPLANATION
XPLANATION
T
....................................................................................................................................................... 13-10
AP
........................................................................................................................................................ 15-8
IMER
..................................................................................................................................................... 15-9
.................................................................................................................................................... 15-2
NTERFACE
.................................................................................................................................................. 13-2
.................................................................................................................................................. 14-2
.............................................................................................................................................. 14-37
M
R
M
ODE
EGISTERS
ODE
........................................................................................................................................ 13-4
........................................................................................................................................ 14-4
...................................................................................................................................... 13-8
.................................................................................................................................... 13-7
.................................................................................................................................... 15-3
........................................................................................................................... 14-20
v
Toshiba RISC Processor
TX4939