TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 305

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
14.3.11. Dynamic Chain Operation
It is possible to add DMA Command Descriptor chains to the DMA Command Descriptor chain while Chain DMA transfer
is in progress. This is performed according to the following procedure.
14.3.12. Interrupts
An interrupt number (10 – 13) of the Interrupt Controller is mapped to each channel. In addition, there are completion
interrupts for when transfer ends normally and error interrupts for when transfer ends abnormally for each channel. When
an interrupt occurs, then the bit that corresponds to either the Normal Interrupt Status field (DIS[3:0]) or the Error
Interrupt Status field (EIS[3:0]) of the DMA Master Control Register (DMMCR) is set.
Figure 14-7 shows the relationship between the Status bit and Interrupt Enable bit for each interrupt cause. Refer to the
explanation for each Status bit for more information regarding each information cause.
Rev. 3.1 November 1, 2005
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Construct the DMA Command Descriptor chain
Construct the DMA Command Descriptor chain to be added to memory.
Add a DMA Command Descriptor chain
Substitute the address of the Command Descriptor at the beginning of the Descriptor Chain to be added
into the Chain Address field of the Descriptor at the end of the DMA Command Descriptor chain that is
currently performing DMA transfer.
Check the Chain Enable bit
Read the value of the Chain Enable bit (CHNEN) of the DMA Channel Control Register (DMCCRn). If
that value is “0”, then write the Chain Address field value of the DMA Command Descriptor that is
indicated by the address stored in the DMA Chain Address Register (DMCHARn).
DMCSRn.NCHNC
DMCSRn.NTRNFC
DMCSRn.STLXFER
DMCSRn.CFERR
DMCSRn.CHERR
DMCSRn.DESERR
DMCSRn.SORERR
DMCCRn.INTENC
DMCCRn.INTENT
DMCSRn.ABCHC
Figure 14-7 DMA Controller Interrupt Signal
DMCCRn.INTENE
14-17
DMMCR.DIS[n]
DMMCR.EIS[n]
Interrupt Controller
(Interrupt No. 10 – 13)
Toshiba RISC Processor
TX4939
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