TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 296

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
14.3.7. Single Address Transfer
Note: The Single Address Transfer is only supported for internal NAND Flash Controller (NDFMC)
This section explains register settings during Single Address transfer (DMCCRn.SNGAD = 1). This applies to the following
DMA Transfer modes.
14.3.7.1. Channel Register Settings During Single Address Transfer
Table 14-2 Channel Register Setting Restrictions During Single Address Transfer shows restrictions of the Channel
Register settings during Single Address transfer. If these restrictions are not met, then a Configuration Error is detected, the
Configuration Error bit (CFERR) of the DMA Channel Status Register (DMCSRn) is set and DMA transfer is not performed.
For Burst transfer, +8, 0, or –8 can be set to the DMA Source Address Increment Register (DMSAIRn). Setting 0 is only
possible during transfer from memory to external I/O. A Configuration Error will result if the value “0” is set during transfer
from external I/O to memory or during Memory Fill transfer.
If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the transfer setting size is 2 bytes
or larger, then set the DMA Source Address Register (DMSARn) with 1 to 3 low-order bits complemented.
Example:
follows below.
During Single Address transfer, the DMA Destination Address Register (DMDARn) and DMA Destination Address
Increment Register (DMDAIRn) settings are ignored.
Rev. 3.1 November 1, 2005
Transfer Setting
Size
(DMCCRn.XFSZ)
16 Double Words
32 Double Words
4 Double Words
8 Double Words
□ External I/O (Single Address) Transfer
□ Memory Fill Transfer
□ If the transfer size is 2 bytes, set the DMSARn with the low-order 1 bit complemented.
□ If the transfer size is 4 bytes, set the DMSARn with the low-order 2 bits complemented.
□ If the transfer size is 8 bytes or larger, set the DMSARn with the low-order 3 bits complemented.
□ DMSAIRn setting is “0” or greater: 0x0_0001_0000
□ DMSAIRn setting is a negative value: 0x0_0001_0007
2 Bytes
4 Bytes
8 Bytes
1 Byte
Table 14-2 Channel Register Setting Restrictions During Single Address Transfer
When the transfer address is 0x0_0001_0000, the DMA Source Address Register (DMSARn) is as
DMSARn[2:0]
DMSAIRn is “0” or
greater
**0
*00
000
000
***
DMSAIRn setting is a
negative value
14-8
**0
*00
111
111
***
DMSAIRn[2:0]
8/0/-8
**0
*00
000
***
Toshiba RISC Processor
DMCNTRn[2:0]
**0
*00
000
000
***
TX4939
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