TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 579

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SIO
19.4.1. Line Control Register 0,1,2,3
Rev. 3.1 November 1, 2005
This register specifies the format of asynchronous transmission/reception data.
R/WUB TWUB UODE
R/W
31
15
0
(SILCR0, SILCR1, SILCR2, SILCR3)
R/W
14
1
Channel
SIO0
SIO1
SIO2
SIO3
R/W
13
0
12
Address Offset
0xF300
0xF400
0xF380
0xF480
Table 19-6 Address offsets for Line Control Register in TX4939
Reserved
Figure 19-6 Line Control Register
Mnemonic
SILCR0
SILCR1
SILCR2
SILCR3
Reserved
19-13
7
SCS
R/W
010
Register Name
Line Control Register 0
Line Control Register 1
Line Control Register 2
Line Control Register 3
6
5
UEPS UPEN USBL
R/W
4
0
R/W
3
0
R/W
Toshiba RISC Processor
2
0
1
UMODE
R/W
00
16
0
: Initial value
: Initial value
: Type
: Type
TX4939
19
19