TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 580

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SIO
Rev. 3.1 November 1, 2005
Bit
31:16
15
14
13
12:8
7:5
4
3
2
1:0
Mnemonic
RWUB
TWUB
UODE
SCS
UEPS
UPEN
USBL
UMODE
Field Name
Reserved
Receive Wake
Up Bit
Transmit Wake
Up Bit
Open Drain
Enable
Reserved
Clock Select
Even Parity
Select
Parity Check
Enable
Stop Bit Length
Mode
Description
Wake Up Bit for Receive (Default: 0)
When in the Multi-Controller System mode, this field selects whether to receive
address (ID) frames whose Wake Up bits (WUB) are “1” or to receive data frames
whose Wake Up bits (WUB) are “0”. This value is undefined when not in the
Multi-Controller System mode.
0: Receive data frames.
1: Receive address (ID) frames.
Wake Up Bit for Transmit (Default: 1)
When in the Multi-Controller System mode, this field specifies the Wake Up bit
(WUB). This value is undefined when not in the Multi-Controller System mode.
0: Data frame transfer (WUB = 0)
1: Address (ID) frame transfer (WUB = 1)
TXD Open Drain Enable (Default: 0)
This field selects the output mode of the TXD signal. When in the Multi-Controller
System mode, the Slave Controller must set the TXD signal to Open Drain.
0: Totem pole output
1: Open drain output
SIO Clock Select (Default: 010)
This field selects the serial transfer clock. The clock frequency that is the serial
transfer clock divided by 16 becomes the baud rate (bps).
000: Internal clock (IMBUSCLK)
001: Baud rate generator output that divided IMBUSCLK
010: Internal Baud rate clock0 (SCLK0)
011: Baud rate generator output that divided SCLK0
100: Internal Baud rate clock1 (SCLK1)
101: Baud rate generator output that divided SCLK1
others: Reserved
SIO Even Parity Select (Default: 0)
This field selects the parity mode.
0: Odd parity
1: Even parity
SIO Parity Enable (Default: 0)
This field selects whether to perform the parity check. This bit must be cleared in
multidrop systems (i.e., when the UMODE field is 10 or 11.)
0: Disable the parity check
1: Enable the parity check
SIO Stop Bit Length (Default: 0)
This field specifies the stop bit length.
0: 1 bit
1: 2 bit
SIO Mode (Default: 00)
This field sets the data frame mode.
00: 8-bit data length
01: 7-bit data length
10: Multi-Controller 8-bit data length
11: Multi-Controller 7-bit data length
Table 19-7 Line Control Register
19-14
Toshiba RISC Processor
R/W
⎯
R/W
R/W
R/W
⎯
R/W
R/W
R/W
R/W
R/W
TX4939
19
19