TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 355

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DDR
DDR_CTL_21 = 0x80A8
DDR_CTL_22 = 0x80B0
DDR_CTL_23 = 0x80B8
Rev. 3.1 November 1, 2005
Name
REG_DIMM_ENABLE
-
DLL_BYPASS_MODE
-
Name
ADDR_PINS
-
COLUMN_SIZE
-
Name
APREBIT
-
-
-
Bits
0:0
7:1
8:8
15:9
Bits
2:0
7:3
10:8
15:11
Bits
3:0
7:4
13:8
15:14
Default
0x0
-
0x0
-
Default
0x0
-
0x0
-
Default
0x0
-
-
-
Range
0x0-0x1
-
0x0-0x1
-
Range
0x0-0x7
-
0x0-0x7
-
Range
0x0-0xf
-
-
-
15-25
Description
Enable registered DIMM operation of the controller.
This register controls the address and command pipeline of the
controller when configured for register DIMM operations.
0 = Normal non registered operation.
1 = Enable register DIMM operation.
Reserved
Enable the DLL bypass feature of the controller.
When set to 1, the values programmed into dll_dqs_delay_x,
dqs_out_shift, and wr_dqs_shift become absolute values rather
than fractional values of delays in the delay chains. In this mode the
DLL locking mechanism is bypassed. If the delay programmed into
the delay registers is greater than the number of delay elements in
the delay chain, then the delay is set to the maximum number of
delay elements in the delay chain.
0 = Normal operational mode
1 = Bypass DLL master delay line.
Reserved
Description
Number of address pins used by DRAM devices.
The difference between the maximum number of address pins (14)
and the actual number of address pins on the device connected to
the controller. The user address is automatically shifted so that the
user address space is mapped contiguously into the memory map
based upon the value of this parameter.
For more detail, see Section 15.13.
Reserved
Number of column bits used for DRAM devices.
The difference between the maximum column width (12) and the
actual number of column pins in the devices connected to the
controller. The user address is automatically shifted so that the
user address space is mapped contiguously into the memory map
based upon the value of this parameter. For more detail see
Section 15.13..
Reserved
Description
Location of autoprecharge bit in DRAM address.
The bit position for the auto precharge signal for the DDR SDRAM
device connected to the controller.
Reserved
Reserved
Reserved
Toshiba RISC Processor
TX4939
15
15