TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 473

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
17.3.3.18. Interrupt Control Register (C98h)
Rev. 3.1 November 1, 2005
BIT
Bit[15]:
Bit[14]:
Bit[13]:
Bit[12]:
Bit[11]:
Bit[10]:
Bit[9]:
Bit[8]:
Bit[7]:
Bit[6]:
Error INT
Error INT
Address
Address
Bit 15
Bit 7
Mask
R/W
R/W
0
0
NAME
Mask Address Error
INT
Mask Reach Multiple
INT
Mask DEV Timing
Error
Mask Ultra DMA DEV
Terminate
Mask Timer INT
Mask Bus Error
Mask Data Transfer
End
Mask Host INT
Address Error INT
Reach Multiple INT
Mask Reach
Multiple
Multiple
Bit 14
Reach
Bit 6
R/W
R/W
INT
INT
0
0
Timing Error
DEV Timing
Mask DEV
Bit 13
Bit 5
Error
R/W
R/W
0
0
Figure 17-23 Interrupt Control Register
Description
Interrupt mask. You can prevent the INTN signal asserting by setting this bit “1”. The
interrupt indicates that this Controller is write-accessed with address where any
registers do not exist.
Bit [7](Address Error INT) can be set regardless of this bit.
Interrupt mask. You can prevent the INTN signal asserting by setting this bit “1”. The
interrupt indicates PIO transfer is in the Break state.
Bit [6](Reach Multiple INT) can be set regardless of this bit.
Interrupt mask. You can prevent the INTN signal asserting by setting this bit “1”. The
interrupt indicates timing of a control signal from the device is out of spec. when
performing data transfer with the device.
Bit [5](DEV Timing Error) can be set regardless of this bit.
Interrupt mask. You can prevent the INTN signal asserting by setting this bit “1”. The
interrupt indicates the device terminated Ultra DMA transfer.
Bit [4](Ultra DMA Terminate) can be set regardless of this bit.
Interrupt mask. You can prevent the INTN signal asserting by setting this bit “1”. The
interrupt indicates the Host Reset timer reached the defined value.
Bit [3](Timer INT) can be set regardless of this bit.
Interrupt mask . You can prevent the INTN signal asserting by setting this bit “1”. The
interrupt indicates the Bus error occurred.
Bit [2](Bus Error) can be set regardless of this bit.
Interrupt mask . You can prevent the INTN signal asserting by setting this bit “1”. The
interrupt indicates data transfer ended.
Bit [1](Data transfer End) can be set regardless of this bit.
Interrupt mask . You can prevent the INTN signal asserting by setting this bit “1”. The
interrupt indicates the INTRQ signal from the device is active.
Bit [0](Host INT) can be set regardless of this bit.
registers do not exist. Setting “1” to this bit clears this interrupt status.
Interrupt status that indicates PIO transfer is in the Break state. Setting “1” to this bit
clears this interrupt status.
Interrupt status that indicates this Controller is write-accessed with address where any
Table 17-4 Interrupt Control Register
Mask Ultra
DMA DEV
Ultra DMA
Terminate
Terminate
Bit 12
Bit 4
R/W
DEV
R/W
0
0
17-19
Mask Timer
Timer INT
Bit 11
Bit 3
R/W
R/W
INT
0
0
Mask Bus
Bus Error
Bit 10
Bit 2
Error
R/W
R/W
0
0
Toshiba RISC Processor
Data Transfer
Transfer End
Mask Data
Bit 9
Bit 1
R/W
End
R/W
0
0
Mask Host
Host INT
Bit 8
Bit 0
R/W
R/W
INT
0
0
TX4939
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