MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 111

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

The following pseudocode explains basic MAC or MSAC instruction functionality. This example
is presented as a case statement covering the three basic operating modes with signed integers,
unsigned integers, and signed fractionals. Throughout this example, a comma-separated list in
curly brackets, {}, indicates a concatenation operation.
switch (MACSR[6:5])
{
Freescale Semiconductor
• The overflow (V) flag is handled differently. It is set if the complete product cannot be
• For the MAC design, the assembler syntax of the MAC (multiply and add to accumulator)
• The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where
case 0:
if (MACSR.OMC == 0 || MACSR.PAVx == 0)
represented as a 40-bit value (this applies to 32 × 32 integer operations only) or if the
combination of the product with an accumulator cannot be represented in the given number
of bits. The EMAC design includes an additional product/accumulation overflow bit for
each accumulator that are treated as sticky indicators and are used to calculate the V bit on
each MAC or MSAC instruction. See
and MSAC (multiply and subtract from accumulator) instructions does not include a
reference to the single accumulator. For the EMAC, it is expected that assemblers support
this syntax and that no explicit reference to an accumulator is interpreted as a reference to
ACC0. These assemblers would also support syntaxes where the destination accumulator
is explicitly defined.
<<1 indicates a left shift and >>1 indicates a right shift. The shift is performed before the
product is added to or subtracted from the accumulator. Without this operator, the product
is not shifted. If the EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and
no shift is performed. Because a product can overflow, the following guidelines are
implemented:
— For unsigned word and longword operations, a zero is shifted into the product on right
— For signed, word operations, the sign bit is shifted into the product on right shifts unless
— For all left shifts, a zero is inserted into the lsb position.
shifts.
the product is zero. For signed, longword operations, the sign bit is shifted into the
product unless an overflow occurs or the product is zero, in which case a zero is shifted
in.
then {
MACSR.PAVx = 0
/* select the input operands */
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {sign-extended Ry[31], Ry[31:16]}
then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]}
/* MACSR[S/U, F/I] */
/* signed integers */
else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]}
if (U/Lx == 1)
MCF5271 Reference Manual, Rev. 2
Section 4.4.1, “MAC Status Register
EMAC Instruction Set Summary
(MACSR).”
4-15