MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 534

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Symmetric Key Hardware Accelerator (SKHA)
The value written to the IV/Nonce registers will be replaced with the running initialization vector,
IV, (CBC mode) or running counter (CTR mode) once processing begins.
If any context registers are read prior to the SKSR[DONE] bit being set, an early read error,
SKESR[ERE], will be generated and an interrupt request will be sent to the interrupt controller (if
ERE is not masked).
28.3
At the top level, the SKHA consists of seven functional blocks: The input FIFO, the output FIFO,
transmit FIFO interface, receive FIFO interface, internal bus interface, top control and the SKHA
logic.
28-16
Functional Description
AES-CTR
Algorithm
Table 28-8. SKHA Context Register Definitions (Continued)
/Mode
1
Figure 28-15. SKHA Block Diagram
Counter*
2
*Must be written at start of new message
MCF5271 Reference Manual, Rev. 2
Input FIFO
3
Transmit
SKHA Context Register n (32-bits each)
4
Internal Bus Interface
Internal Bus
SKHA Logic
Top Control
Internal Bus
—
5
—
6
Output FIFO
—
7
Receive
—
8
—
9
10
—
11
—
Freescale Semiconductor
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