MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 308

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

External Interface Module (EIM)
occur when CLKOUT is low. The state transition diagram for basic and fast termination read and
write cycles are shown in
Table 17-4
17-6
S0
S1
S2
S3
S4
State
All
All
Fast
Termination
Read/write
(skipped fast
termination)
Write
Read/write
(skipped for
fast
termination)
Read
All
Read
(including
fast-terminati
on)
describes the states as they appear in subsequent timing diagrams.
Cycle
Figure 17-4. Data Transfer State Transition Diagram
High
Low
High
Low
High
CLKOUT
Figure
Next Cycle
S5
S4
The read or write cycle is initiated in S0. On the rising edge of CLKOUT, the
MCF5271 places a valid address on the address bus and drives R/W high for a
read and low for a write, if it is not already in the appropriate state. The MCF5271
asserts TIP, TSIZ[1:0], and TS on the rising edge of CLKOUT.
The appropriate CSn, BSn, and OE signals assert on the CLKOUT falling edge.
TA must be asserted during S1. Data is made available by the external device and
is sampled on the rising edge of CLKOUT with TA asserted.
TS is negated on the rising edge of CLKOUT in S2.
The data bus is driven out of high impedance as data is placed on the bus on the
rising edge of CLKOUT.
The MCF5271 waits for TA assertion. If TA is not sampled as asserted before the
rising edge of CLKOUT at the end of the first clock cycle, the MCF5271 inserts wait
states (full clock cycles) until TA is sampled as asserted.
Data is made available by the external device on the falling edge of CLKOUT and
is sampled on the rising edge of CLKOUT with TA asserted.
The external device should negate TA.
The external device can stop driving data after the rising edge of CLKOUT.
However data could be driven through the end of S5.
Table 17-4. Bus Cycle States
17-4.
MCF5271 Reference Manual, Rev. 2
Termination
Fast
S0
S3
Wait
States
Description
S1
S2
Basic
Read/Write
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