MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 422

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MCF5270CAB100

Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5270CAB100

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Queued Serial Peripheral Interface (QSPI) Module
23.1.3.1 Interface and Signals
The module provides access to as many as 15 devices with a total of seven signals: QSPI_DOUT,
QSPI_DIN, QSPI_CLK, QSPI_CS0, QSPI_CS1, QSPI_CS2, and QSPI_CS3.
Peripheral chip-select signals, QSPI_CS[3:0], are used to select an external device as the source
or destination for serial data transfer. Signals are asserted at a logic level corresponding to the
value of the QSPI_CS[3:0] bits in the command RAM whenever a command in the queue is
executed. More than one chip-select signal can be asserted simultaneously.
Although QSPI_CS[3:0] will function as simple chip selects in most applications, up to 15 devices
can be selected by decoding them with an external 4-to-16 decoder.
23-2
Internal Bus
QSPI Data Output (QSPI_DOUT)
QSPI Data Input (QSPI_DIN)
Queue Control
Control Logic
Comparator
End Queue
Internal Bus
Clock (f
Table 23-1. QSPI Input and Output Signals and Functions
Counter
Control
Pointer
Pointer
Queue
Block
Status
Delay
Regs
Regs
Signal Name
sys/2
)
Figure 23-1. QSPI Block Diagram
Divide by 2
MCF5271 Reference Manual, Rev. 2
Address
Register
Done
4
QSPI
Logic
Array
4
Configurable
N/A
Hi-Z or Actively Driven
Command
Select
Chip
4
4
Baud Rate
Generator
80-Byte
QSPI
RAM
msb
8/16 Bit Shift Reg.
Rx/Tx Data Reg.
Serial data output from QSPI
Serial data input to QSPI
Function
lsb
4
Register
Freescale Semiconductor
QSPI
Data
QSPI_DIN
QSPI_DOUT
QSPI_CS[3:0]
QSPI_CLK

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